Quick Presets

Layer Assignment
L1 SIG
L2 GND
L3 SIG
L4 PWR
L5 SIG
L6 SIG
L7 GND
L8 SIG
L9 PWR
L10 SIG

Copper Layers

Prepreg Layers (5)

Core Layers (4)

Total Board Thickness
1.600mm
1600 ?m
vs 1.6mm
+0 ?m
Copper (10L)
350 ?m
Prepreg (5L)
642 ?m
Core (4L)
600 ?m

Stackup Visualization

L1 – Top SignalSIG 35?m
Prepreg 1 (PP1) 114?m
L2 – GND PlaneGND 35?m
Core 1 (FR-4) 100?m
L3 – Inner SignalSIG 35?m
Prepreg 2 (PP2) 114?m
L4 – PWR PlanePWR 35?m
Core 2 (FR-4) 200?m
L5 – Inner SignalSIG 35?m
Prepreg 3 (PP3) – Center 185?m
L6 – Inner SignalSIG 35?m
Core 3 (FR-4) 200?m
L7 – GND PlaneGND 35?m
Prepreg 4 (PP4) 114?m
L8 – Inner SignalSIG 35?m
Core 4 (FR-4) 100?m
L9 – PWR PlanePWR 35?m
Prepreg 5 (PP5) 114?m
L10 – Bottom SignalSIG 35?m
SOLDER MASK (BOTTOM)
Outer Signal
Inner Signal
GND Plane
PWR Plane
Prepreg
Core
? Common 10-Layer Targets
1.2mm: High-density mobile, FPGA applications
1.6mm: Standard multilayer (most common)
2.0mm: Industrial, server boards
2.4mm – 3.0mm: Backplanes, heavy copper
? 10-Layer Design Strategy
Symmetric Structure: L1-L5 mirrors L6-L10 for balanced warpage control.
High-Speed Routing: L3, L5, L6, L8 are stripline layers with excellent shielding.
Power Integrity: Distributed GND (L2, L7) and PWR (L4, L9) minimize loop inductance.
? Impedance Reference
L1 & L10: Microstrip (ref: L2, L9)
L3: Stripline (ref: L2 + L4)
L5 & L6: Broadside-coupled stripline
L8: Stripline (ref: L7 + L9)