Quick Presets

Layer Assignment (10 Signal + 5 GND + 5 PWR)
L1 SIG
L2 GND
L3 SIG
L4 PWR
L5 SIG
L6 GND
L7 SIG
L8 PWR
L9 SIG
L10 GND
L11 PWR
L12 SIG
L13 GND
L14 SIG
L15 PWR
L16 SIG
L17 GND
L18 SIG
L19 PWR
L20 SIG

Copper Layers (20)

Prepreg Layers (10)

Core Layers (9)

Total Board Thickness
3.500mm
3500 ?m
vs 3.5mm
+0 ?m
Copper (20L)
700 ?m
Prepreg (10L)
1310 ?m
Core (9L)
1600 ?m
10
Signal
5
GND
5
PWR
8
Stripline
2
Microstrip

Stackup Visualization

L1 – Top SignalSIG 35?m
PP1 114?m
L2 – GNDGND 35?m
Core 1 100?m
L3 – SignalSIG 35?m
PP2 114?m
L4 – PWRPWR 35?m
Core 2 200?m
L5 – SignalSIG 35?m
PP3 114?m
L6 – GNDGND 35?m
Core 3 200?m
L7 – SignalSIG 35?m
PP4 114?m
L8 – PWRPWR 35?m
Core 4 200?m
L9 – SignalSIG 35?m
PP5 (Center) 185?m
L10 – GND (Center)GND 35?m
Core 5 (Center) 200?m
L11 – PWR (Center)PWR 35?m
PP6 185?m
L12 – SignalSIG 35?m
Core 6 200?m
L13 – GNDGND 35?m
PP7 114?m
L14 – SignalSIG 35?m
Core 7 200?m
L15 – PWRPWR 35?m
PP8 114?m
L16 – SignalSIG 35?m
Core 8 200?m
L17 – GNDGND 35?m
PP9 114?m
L18 – SignalSIG 35?m
Core 9 100?m
L19 – PWRPWR 35?m
PP10 114?m
L20 – Bottom SignalSIG 35?m
SOLDER MASK (BOTTOM)
Outer SIG
Inner SIG
GND
PWR
Prepreg
Core
? 20L Targets
3.2mm: High-density HDI
3.5mm: Standard 20L
4.0-4.5mm: Server/HPC
5.0mm+: Backplane
? Impedance
Microstrip: L1¡úL2, L20¡úL19
Stripline: All inner SIG
Center: L10?L11 tightly coupled
? Power Integrity
5 GND: Distributed ref planes
5 PWR: Multi-rail support
L10-L11: Ultra-low Z decoupling
? Applications
HPC: GPU/TPU accelerators
Network: 400G+ switches
Server: Multi-socket CPU
? 20-Layer Design Strategy
10 Signal Layers: L1, L3, L5, L7, L9, L12, L14, L16, L18, L20 ¡ª Ultra-high routing density for complex BGA fanout (0.3mm pitch), HBM3 memory, 224G PAM4 / 112G NRZ SerDes, and PCIe Gen6.
5 GND Planes: L2, L6, L10, L13, L17 ¡ª Ground reference within 4 layers of every signal; L10 center GND provides symmetry axis and shielding.
5 PWR Planes: L4, L8, L11, L15, L19 ¡ª Support 6+ voltage rails with splits (VCore, VIO, VDDA, VDDQ, VPP, VCCSA); L10-L11 form ultra-low-inductance decoupling pair.
Via Strategy: Requires sequential lamination with blind/buried vias and microvias (stacked or staggered); via aspect ratio typically 12:1 max.
Material: Consider low-loss materials (Megtron 6/7, Tachyon, I-Tera MT40) for high-speed lanes >25Gbps.
Symmetry: Structure symmetric about Core 5 center for optimal CTE matching, warpage control (<0.5%), and reliable BGA/LGA reflow.